Voltage drop, also called IR drop, is the voltage reduction that occurs on power supply networks. The IR drop may be static or dynamic and results from the existence of non-ideal elements—the resistance within the power and ground supply wiring and the capacitance between them. While static voltage drop considers only the average currents, dynamic voltage drop considers current waveforms within clock cycles and has an RC transient behavior. Similar effects may be found in ground wiring, usually referred as ground bounce, whereby current flows back to the ground/Vss pins causing its voltage to fluctuate. Both effects contribute to lower operating voltages within devices (e.g., logic cells/gates in digital circuits), which in general increases the overall time response of a device and might cause operational failures.
The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the physical design methodology process of integrated systems. In modern electronic circuits, geometries become smaller; clock frequencies increase; and on-chip interconnections gain increased importance in the prediction of performance. Nonetheless, it has been found that from 0.13 μm and bellow, ICs are more susceptible to IR drop, which requires some degree of built-in fault-tolerance and a careful design planning. Meanwhile, increased power demanded on ever shrunk chip size further exacerbates the problem because a significant number of devices may become active in a short period of time and drawing current from close regions of the power grid.
Unfortunately, most conventional electronic circuit design tools focus on post-layout verification of the power grid when the entire chip design is complete and detailed information about the parasitics of the physical designs and the currents drawn by the transistors are known. IR drop problems revealed at this stage are usually very difficult or expensive to fix so the conventional methodologies help to design an initial electronic design and refine it iteratively at various design stages. In other words, the conventional circuit synthesis step is followed by layout synthesis and each step is carried out independent of the other. This is again followed by a physical or formal verification step to check whether the desired performance goals have been achieved after layout generation and extraction. These steps are carried out iteratively in such conventional approaches till the desired performance goals are met.
Thus, there exists a need for implementing electronic circuit designs with IR-drop awareness early in the design stage.